Hence the mirrored value in the model is the latest known value in the design. Mirrored ValueĮvery time a read or a write operation occurs on the design, the mirrored values for that particular register will be updated. For example, if we want the register REG_STAT in the design to have a value of 0x1234_5678, then the desired value of that register has to be set to 0x1234_5678 within the model and an update task should be called for this to be reflected in the design. In other words, the model has an internal variable to store a desired value that can be updated later in the design. This is the value we would like the design to have. There are two kinds of variables inside the register within a model. We can perform read and write operations on the design using a register model object.Įvery register in the model corresponds to an actual hardware register in the design. A register model is an entity that encompasses and describes the hierarchical structure of class objects for each register and its individual fields. So we'll simply use existing UVM RAL (Register Abstraction Layer) classes to define individual fields, registers and register-blocks. We already have an idea of how registers are laid out in a memory map from Introduction.
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